What's CPO and the ecosystem
Optical I/O, Co-Packaged Optics (CPO), and Traditional Interconnects
Migration from Copper to Optics in Switch ASICs
1. Introduction
As bandwidth demands scale into the multi-terabit era, traditional electrical interconnects on PCBs are hitting fundamental limits in power, signal integrity, and reach. This has driven the emergence of:
Pluggable optics (today’s standard)
Co-Packaged Optics (CPO)
Full Optical I/O (integrated photonics)
While the transition is already underway in switch ASICs, GPUs/TPUs follow a different trajectory due to architectural differences.
2. Three Interconnect Architectures
2.1 Traditional Pluggable Optics
Architecture:
ASIC sends high-speed electrical signals (SerDes)
Signals travel across PCB (long traces)
Reach pluggable module (QSFP/OSFP)
Converted to optical and transmitted via fiber
Key Characteristics:
Long electrical paths (10–30 cm or more)
High power consumption
Signal integrity challenges
Mature ecosystem
Mental Model:
Chip → long copper → optics
2.2 Co-Packaged Optics (CPO)
Architecture:
Optical engines placed inside the same package as the ASIC
Electrical connections reduced to millimeters
Optical signals exit package directly to fiber
Key Characteristics:
Very short electrical paths
Improved power efficiency
Reduced PCB complexity
Increased thermal challenges
Mental Model:
Chip → tiny copper → optics
2.3 Full Optical I/O (Integrated Photonics)
Architecture:
Optical interfaces integrated into or tightly coupled to the compute die
Minimal or no high-speed electrical I/O leaving the package
Direct fiber connections from package
Key Characteristics:
Eliminates long electrical interconnects
Highest potential efficiency and bandwidth density
Enables new system architectures (disaggregation)
Still emerging technology
Mental Model:
Chip → light directly
In Summary
| Feature | Pluggable Optics | CPO | Optical I/O |
|---|---|---|---|
| Electrical trace length | Long | Very short | Minimal |
| Optical location | External module | In-package | Near/on-die |
| Power efficiency | Lowest | Improved | Best (potential) |
| PCB complexity | High | Reduced | Low |
| Thermal complexity | Moderate | High | Very high |
| System maturity | Mature | Emerging | Early-stage |
3. Why CPO Works So Well for Switch ASICs
Switch ASICs are fundamentally:
I/O-bound
Designed to move data over long distances (rack-to-rack)
Benefits of CPO for Switches:
Eliminates long PCB traces
Reduces SerDes power
Improves signal integrity
Scales bandwidth efficiently (51.2T → 102.4T and beyond)
System Impact:
Fiber attaches directly to package
PCB mainly handles:
Power delivery
Control signals
Mechanical support
 |
| Broadcom BCM78919 |
4. Why GPUs/TPUs Are Different
GPUs and TPUs are compute-bound systems, not purely I/O devices.
4.1 Local Bandwidth Dominates
Most data movement happens:
Between compute die and HBM
Across short-reach interconnects (e.g., NVLink-like fabrics)
These links are:
Extremely short
Highly optimized
Already efficient in copper
4.2 Current GPU System Architecture
Typical flow:
GPU → PCIe/NVLink → NIC/Switch → Pluggable Optics → Fiber
Key point:
GPUs do not directly drive long-reach optical links today
5. Where Optical Technologies Matter for GPUs
5.1 Near-Term: Network Edge (NICs and Switches)
Optics remains in:
NICs
Switches
GPUs remain electrically connected
5.2 Mid-Term: Tighter Integration
Optical interfaces move closer to compute
Possible co-packaging with NIC or accelerator
5.3 Long-Term: Full Optical I/O
Emerging concept:
GPUs with integrated optical interfaces
Direct optical communication between:
GPUs
Memory pools
Accelerators
6. Disaggregated AI Systems (Future Direction)
Optical I/O enables a major architectural shift:
Traditional Node:
Fixed GPU + local HBM
Limited by board-level interconnect
Future Rack-Scale System:
Compute and memory separated
Connected via optical fabric
Example:
Compute tray (GPUs with optical I/O)
Memory tray (pooled HBM)
Optical fabric switch
Benefits:
Resource pooling
Higher utilization
Scalable bandwidth
Flexible system design
The industry is moving from:
Copper-limited systems → Optically interconnected systems
7. Competitive landscape around CPO in switch silicon.
7.1) The core shift: why switch ASICs are ground zero
This isn’t just “better optics”—it’s a forced migration:
100G → 200G/lane → 400G/lane
PCB copper loss explodes
Retimers/DSPs burn too much power
👉 Result:
CPO isn’t optional beyond ~200G/lane—it’s inevitable
That’s why:
First real deployments = switches, not compute
Hyperscalers are already validating CPO switch platforms
7.2) The real player stack (who actually matters)
Think in layers:
A. Tier 1: Switch ASIC + system control (the winners—so far)
Broadcom
Clear leader today
Shipping multi-generation CPO (51.2T → 102.4T)
Proven hyperscaler deployments (Meta, etc.)
Tight vertical integration (ASIC + optics ecosystem)
👉 Status: Firmly in the lead
NVIDIA
Mellanox heritage (InfiniBand + Ethernet switches)
Aggressive push into CPO for AI fabrics
Strong system-level advantage (GPU + network stack)
👉 Status: #2 but strategically dangerous
Marvell Technology
Strong in DSP + optical PHY
Recently doubled down (e.g., Celestial AI acquisition) (lightcounting.com)
Deep hyperscaler relationships (esp. AWS)
👉 Status: Fast follower, closing gap
Cisco Systems
System-level player (not pure silicon leader)
Leveraging enterprise footprint
👉 Status: Relevant, but not leading the silicon race
B. Tier 2: Photonics / optical engine disruptors
These are critical because CPO = optics + silicon.
Ayar Labs
Probably the most important startup in this space
Optical I/O chiplets (TeraPHY)
Partnerships with ASIC vendors (GUC, Alchip) (Ayar Labs)
Heavy funding + strategic investors (incl. major chip companies) (AInvest)
👉 Status: Key enabler, not a switch vendor—but hugely influential
Others in this layer:
Ranovus
Lightmatter
Celestial AI
👉 Status:
Competing architectures (silicon photonics, chiplet optics)
Likely consolidation (already started—see Marvell move)
C. Tier 3: Regional / vertical challengers
Huawei
Strong domestic push (China)
Government-backed ecosystem
InnoLight Technology
Optical module expertise moving toward CPO
👉 Status: Regionally strong, globally constrained (for now)
7.3) Who’s actually “in” vs “at risk”
CLEAR WINNERS (next 3–5 years)
1. Broadcom
Shipping + deployed + ecosystem lock-in
Already at 3rd-gen CPO (lightcounting.com)
👉 Hard to displace unless:
hyperscalers go fully custom
2. NVIDIA
Owns the AI system stack
Can force adoption via DGX / SuperPOD-like systems
👉 Their advantage isn’t optics—it’s system control
STRONG CONTENDERS
Marvell
Making aggressive moves (acquisitions, DSP strength)
Positioned well if hyperscalers diversify away from Broadcom
👉 Could become #2 in merchant silicon
Ayar Labs (and similar)
If optical I/O wins → they win
If CPO stays “incremental” → they stay niche
👉 High upside, high uncertainty
AT RISK / SQUEEZED
Traditional pluggable optics ecosystem
DSP vendors
Module vendors
Why:
CPO removes:
Long electrical links
External DSP-heavy modules
👉 This is the real disruption layer
Smaller ASIC vendors
No scale to:
co-design optics + packaging
support hyperscaler requirements
👉 Likely outcomes:
Acquired
Become niche
Or exit
7.4) The uncomfortable truth: timeline reality
Despite all the hype:
Large-scale CPO deployment: ~2028–2030 (EDN)
Pluggables still competitive today
👉 Translation:
Nobody is “out soon”—but positioning is happening now
7.5) What actually determines winners (not obvious)
It’s NOT just optics tech.
The real differentiators:
1. Packaging capability
Integrating:
ASIC
optics
thermals
fiber attach
👉 This is brutally hard
2. Hyperscaler relationships
Google, Meta, AWS decide winners
Not enterprise buyers
3. Ecosystem control
Firmware
system design
supply chain
👉 This is why Broadcom/NVIDIA dominate
7.6) Bottom line (no fluff)
CPO is inevitable for switch ASICs
Broadcom leads, NVIDIA threatens, Marvell chases
Photonics startups are the wildcard
Real disruption hits the pluggable optics ecosystem first—not GPUs
8. Supply chain anatomy of a Broadcom CPO system
8.1) What Broadcom actually owns vs outsources
From their own disclosures:
Broadcom integrates the optical engines + switch ASIC in one package (Broadcom Inc.)
They rely on a “comprehensive ecosystem of passive optical components, interconnects, and system partners” (Broadcom Inc.)
👉 Translation:
Broadcom controls system architecture + integration, not every component
8.2) The CPO stack (clean decomposition)
[ External Laser Source ]
↓
[ Fiber coupling / connectors ]
↓
[ Optical Engine (PIC + modulators + PDs) ]
↓
[ Package / interposer ]
↓
[ Switch ASIC (Broadcom Tomahawk) ]
Now let’s map who supplies what.
8.3) LASERS (light source layer)
Architecture reality
Broadcom CPO does NOT put lasers inside the switch package
Uses external laser sources (ELS / RLM)
Light is fed via fiber into the package
👉 This is consistent with:
thermal constraints
serviceability (replaceable lasers)
Likely suppliers
Tier-1 candidates:
Lumentum
Coherent Corp.
Applied Optoelectronics (AAOI)
These companies specialize in:
high-power CW lasers
narrow linewidth sources for silicon photonics
Supporting evidence
Broadcom explicitly supports remote laser modules (RLM) in its systems (Broadcom Inc.)
External laser model is industry standard for CPO designs (thermal + reliability)
Key takeaway
👉 Laser vendors (AAOI, Lumentum, Coherent) are:
Outside the package—but absolutely critical
8.4) PIC / OPTICAL ENGINE (the core of CPO)
This is where things get interesting.
What Broadcom does
Designs silicon photonics optical engines in-house
Integrates:
modulators
photodetectors
waveguides
electronic drivers
Evidence:
“silicon photonics based optical engines” integrated with switch (Broadcom Inc.)
Foundry / fabrication:
TSMC (very likely)
Tower Semiconductor (TSEM, common in photonics ecosystem) an Isreal Company
These fabs:
manufacture silicon photonics wafers
provide process nodes optimized for photonics
Potential ecosystem contributors
(depending on design partitioning)
Ayar Labs (in other systems, not Broadcom primary)
Ranovus
👉 But:
Broadcom is more vertically integrated here than most people realize
Key takeaway
👉 PIC layer is:
Mostly Broadcom-controlled, fabbed by external foundries
8.5) PACKAGING (the hardest and most underestimated layer)
This is the real bottleneck.
What’s required:
Co-packaging ASIC + optical engines
Fiber attach (sub-micron alignment)
Thermal management
High-yield assembly
Named ecosystem partners
From Broadcom announcements:
Fiber + connectors
Corning
fiber + connectivity systems (Broadcom Inc.)
Foxconn Interconnect Technology
sockets, connectors, laser cages (Broadcom Inc.)
System / integration / manufacturing
Delta Electronics 台達電
Micas Networks 銓立光
These build:
full switch systems
cooling + mechanical integration (Broadcom Inc.)
Advanced packaging (inferred but critical)
Likely players:
TSMC
OSATs (ASE, Amkor—industry standard even if not named)
Key insight (this is the real bottleneck)
👉 Packaging is where:
yield is hardest
scaling breaks
differentiation happens
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